1. Field of the Invention
The present invention relates to a mounting technology of electronic information transmission system and more particularly to a system in-package test inspection apparatus for measuring and evaluating high-speed/high frequency electric characteristic of a system in-package (SIP) whose system is established on a structure body loaded with a multiplicity of electronic components such as semiconductor integrated circuit (LSI) chips and the like and a test inspection method.
2. Description of the Related Art
The system in-package (hereinafter referred to as SIP) concerns technology for mounting a plurality of LSI chips in a single package and because high density and high speed electronic system can be constructed using an existing LSI chip, application development thereof onto ubiquitous high function information devices such as mobile phone has been advanced energetically. If classified depending on the configuration, the kinds of the SIP includes, as shown in FIG. 7, chip stack type, package stack type, wafer stack type, plane multi-chip type and the like.
Of the SIPs, the aforementioned package stack type and plane multi-chip type have been actually used and widely applied already.
On the other hand, because in the package stack type, wire between chips is short and high speed transmission can be achieved, its development has been achieved energetically and part thereof has been already utilized. Particularly, the chip stack type has been adopted in a mobile phone in which reduction of the size and intensification of performance have been demanded strongly such as portable phone, digital camera, personal digital assistance (PDA) and the like. The semiconductor device of the chip stack type has been described in, for example, Japanese Patent Application Laid-Open No. 2004-31649.
By the way, the performance required for the SIP has been demanded to be high electric performance and reliability in a frequency range of several GHz to several tens GHz accompanied by intensified performance of the apparatuses and a test inspection apparatus for measuring and evaluating that high speed/high frequency electric performance has been demanded.
Although the test inspection on the aforementioned package stack type and plane multi-chip type can be met by conventional technology, the chip stack type SIP which can be expected to reduce cost largely in the SIPs and is estimated to prevail rapidly has not been yet developed from viewpoints of high speed/high frequency test inspection technology.
FIG. 8 shows an example of the chip stack type SIP. As shown in the same Figure, in the chip stack type SIP 200, a plurality of LSI chips 202, 203, 204, 205 different in size are placed in multi-layers and bonding pads P formed on the respective layers are connected to each other with bonding wire W. In the meantime, input/output signals of the entire SIP 200 are inputted and outputted through soldering balls formed on the bottom face of the LSI package 201.
In such a chip stack type SIP 200, the test inspection of the SIP can be carried out through the soldering ball which is an I/O terminal. However, in the inspection of the high-speed/high-frequency characteristic, no high frequency signal can be transmitted due to an influence of inductance originating form a long wire within the LSI package 201, so that no accurate inspection is enabled.
Although the above-described problem can be solved if a test evaluation signal can be inputted directly into a signal line between the LSI chips, that is, to the bonding pad P or the bonding wire W not through the LSI package 201, the conventional probe cannot be contacted with only an arbitrary signal line because its pitch is very fine. That is, in case of the chip stack type, any inspection signal cannot be inputted from a signal line between stacked LSI chips and in test inspection, the inspection signal needs to be always inputted through the LSI package 201, and consequently, the high speed/high frequency characteristic cannot be inspected at a high precision.